1. Field of the Invention
The subject method and system for optimized circuit autorouting is generally directed to the reliable optimization of an autorouted circuit design. More specifically, the method and system serves to enable selective optimization of an interconnect solution obtained by autorouting while automatically guarding against adverse impact upon the interconnect solution's degree of adherence to applicable design constraints. The subject method and system enable one or more selected constraints pertaining to the autorouted circuit design to be ‘safely’ tightened, thereby improving the autorouted circuit design in measurable terms without jeopardizing its compliance with all applicable design rules and constraints. Programmably implemented measures are taken to recursively enhance a level of optimization relative to user-defined constraints attained by an interconnect solution for the given circuit design, without forfeiting any prior gains made in that regard.
With the advent of printed circuit boards (PCBs) and electronic design automation (EDA), manufacturers have relied increasingly upon autorouter systems to generate, to the extent possible, interconnect solutions for implementing the given circuit designs consistent with all design requirements. Such an autorouter system generally receives as inputs a set of electrical terminals, a net list formed by a set of connections between the terminals, and a set of user-defined constraint instances. The autorouter system operates to generate an interconnect solution which contains a set of routes for the connections defined so as to meet all constraint instances and other applicable design rules. Once it generates an interconnect solution, however, the autorouter system invariably ceases execution.
While an interconnect solution thus generated by an autorouter system may suffice at that stage to meet minimum requirements, it may still fall far short of the optimum circuit design actually permitted by those requirements. For example, an interconnect solution which just manages to satisfy all constraint instances and establish all necessary connections between terminals, may not be sufficiently tolerant to certain unavoidable factors bearing on the circuit design, like manufacturing variations, environmental conditions, material properties, or other factors that the given circuit will be subjected. Moreover, the solution may not leave ample ‘room’ for statistical variations inherent to certain constraint instances.
Circuit designers have consequently tended to over-constrain their circuit designs, artificially specifying limits for constraint instances well beyond that which is electrically required. This practice, coupled with a steady increase in the number of constraints imposed upon a circuit design over the past decades, has often led to over-constrained systems for which an interconnect solution meeting all applicable constraints is not even theoretically possible.
In those cases where they have not altogether abandoned the use of an autorouting system in favor of manual routing for the design, circuit designers have also taken to post-optimizing an autorouted interconnect solution themselves. Consulting the expertise of colleagues in other disciplines (electrical engineering, signal integrity engineering, . . . ), the circuit designer will manually evaluate then tighten or relax certain constraint instances towards a ‘better’ if not ‘best’ solution. This is not without prohibitive challenges.
The autorouting of PCBs early on focused primarily upon minimizing path lengths between connecting pins together to form nets. This necessitated relatively few, mostly distance-based, design rules such as minimum track widths, minimum clearance between objects, and the like. As operational parameters like clock speeds increased, however, additional constraints of timing-based, voltage-based, and other type became increasingly necessary to the point where, in many applications today, most if not all the nets of a circuit design are subject to multiple, often inter-dependent constraints.
The increasing sophistication in the nature of the circuit designs themselves has only exacerbated the situation, with the number and interdependencies of applicable parameters (such as track length, track separation, the associated crosstalk) growing ever more complex. Such is the complexity in many cases that selectively modifying a constraint instance may have considerable unintended effect upon various other constraint instances. It is a daunting challenge even for the most experienced and skilled of circuit designers, and even in applications involving circuit designs of marginal complexity, to manually monitor such unintended effects in full scope. Suitable post-routing optimization of an interconnect solution thus remains far from attainable in many cases today.
In many applications, the certain select constraints are of particular importance to the circuit design than others. The capability to selectively over-constrain that and, possibly, other constraint instances, in a recursive manner would be invaluable to the PCB designer seeking the best possible interconnect solution. Presently, there is no automated means known to reliably evaluate the full potential impact upon the circuit design and its interconnect solution of over-constraining a particular constraint instance. Nor is there a reliable means known by which to automatically assess whether a selective modification to the interconnect solution would in fact improve its overall degree of compliance with applicable constraints.
The only viable alternative heretofore known for reliably assessing the impact of over-constraining a given circuit design is to re-execute the autorouting in its entirety with the circuit design over-constrained in anticipatory manner. There is therefore a need for comprehensive automatic optimization of an autorouted interconnect solution. There is a need for a method and system by which such post-routing optimization of a circuit design is made without adverse impact upon compliance with any applicable constraint.
2. Prior Art
Autorouter systems having post-routing capability for limited manipulation of certain pre-set features are known. These include systems which effect routing passes for reducing the number of resultant via structures. They also include systems which execute track-centering by which a route disposed between two terminals is automatically re-positioned to the half-way point between them, for higher PCB yield.
Although such known systems incorporate apparent improvements as to certain types of constraints, they fail to do so in a manner which guards against potential adverse impact of the apparent improvement upon other constraints. They fail, therefore, to provide any balancing of the possible interdependencies between different constraints. A track-centering change of the type known, for example, could potentially increase crosstalk on a neighboring circuit layer to the point of non-compliance. Likewise, a via-reduction change of the type known could potentially increase track length beyond the corresponding constraint limit.
There is no method or system known which automatically monitors for and guards against such potentially adverse effects of an optimizing change to the interconnect solution. Nor is there any method or system known which does so in a comprehensive and user-selective manner to ensure that an optimizing change does actually improve upon the interconnect solution's overall the degree of compliance with applicable constraints.